1. Field of the Invention
The present invention relates to structural testing of logic integrated circuits, or integrated circuits including logic portions.
2. Discussion of the Related Art
The production of integrated circuits generally includes steps of testing of the produced circuits, once manufactured. These tests are usually of two sorts: structural tests on the one hand, and functional tests on the other hand. Structural tests consist of checking that the circuits do not have physical defects which make them inoperative. Such defects are independent from the applications of the circuits. The functional tests consist of checking, for circuits showing no physical defects, that these circuits operate properly for the applications for which they are meant.
In logic circuits, the effect of physical defects is shown by a fault model on a logic level. The most widely used model is the so-called stuck-at-fault model, in which an electric node of the circuit always keeps the same logic level (in binary logic: the low state for a stuck-at fault at 0 and the high state for a stuck-at fault at 1), independently from the states of the logic signals which control the node. If a two-input AND-type logic gate having an input blocked in the low state (stuck-at fault at 0) is for example considered, the signal provided by the gate will always be in the low state whatever the state of the signal received by the other input.
In order to detect a fault on a node, the node has to be controllable and observable. Ideally, all the nodes of a logic circuit to be tested must be controllable and observable.
The controllability is the ability to impose on each internal node of the logic circuit a given logic state, based on the logic state of the primary inputs/outputs of the circuit. The "primary inputs/outputs of the circuit" refer to the nodes of the circuit which are accessible from the outside of the circuit, that is, directly connected to access pads. The state of these nodes may be controlled (that is, imposed and/or observed) directly by a testing device.
The observability is the ability to propagate the logic states of the internal nodes to pins of the circuit, which renders possible an a posteriori analysis of the circuit structure.
Conventionally, the logic circuits are submitted o)testing patterns. A pattern corresponds to a set of logic states applied to the primary inputs of the circuit, and to a set of logic states supplied by the primary inputs as a response to the states received by the circuit. For a given circuit, the states supplied by the circuit are compared to the expected states, these expected states being calculated based on the logic equations of the circuit and based on all the states supplied to the circuit. There is success if the states supplied by the circuit coincide with the expected states. Any difference indicates that there is a defect in the fabrication of the circuit.
Considering the stuck-at-fault pattern, a test pattern must enable detection of as many stuck-at faults as possible, if present. For this purpose, it is attempted to put on each controllable node of the circuit a logic value and whether the forced value has effectively been taken into account is checked. For example, if a node is blocked in the low state, it requires, to be detected, a pattern which would force it to the high state if it was not blocked. Finally, the test pattern must propagate the effect of the fault to an output where the consequence can be observed (either directly, if the node is accessible, or indirectly if a node placed downstream of the failing node is observed).
For small combinatory circuits, test patterns with a 100% fault coverage (all possible faults are detectable) are relatively easy to develop, even once the circuit is manufactured.
Conversely, the testing of a large sequential circuit is more complicated and may require the application of a complex set of patterns arranged in a specific order. To simplify testing, the implementation of structural tests from as soon as the steps of designing of the circuit structure tend to be taken into account, for example by inserting internal circuits dedicated to the testing in the circuits.
A conventional solution is to insert one or several test shift registers, which generally enables an excellent fault coverage. This (these) test register(s) are formed of flip-flops connected in series to one another, these flip-flops being positioned at the nodes to be tested so as to impose and/or sample the logic states of these nodes.
Flip-flops specifically dedicated to testing may also be used.
Flip-flops used in normal operating mode and in test mode may also be used. This case is illustrated in FIG. 1. In this last case, multiplexing circuits are typically placed at the inputs of these flip-flops in order to selectively connect their input according to the selected mode, that is, according to whether the input must be connected to the output of a flip-flop in test mode, or to another node in normal operating mode. Thus, in FIG. 1, a D flip-flop referenced as BD1 has an input D, an output Q, and two control inputs C1 and C2 for receiving a signal SET for setting to the high state and a signal CLEAR for setting to the low state. Input D is connected to the output of a two-input multiplexer MB1. The inputs of multiplexer MB are connected to two nodes NA and NB. A selection signal S enables to connect the input D of the flip-flop either to node NA or to node NB. Node NA corresponds for example to an output of a circuit LBD of combinatory gates. Node NB corresponds for example to an output of a flip-flop BD2 which can be dedicated to the testing or have, like flip-flop BD1, a input multiplexer. Output Q of flip-flop BD1 is connected to an input of a circuit LBQ of combinatory gates and to an input of a flip-flop BD3 via a multiplexer MB3. In test mode, the input D of flip-flop BD1 is connected to node NB and its output Q is connected to the input of flip-flop BD3. In normal operating mode, input D is connected to node NA.
A test sequence can be broken up into four steps:
1--in test mode, by a series of shiftings in the flip-flops forming the test register(s), the states to be imposed are brought to the desired nodes. The circuit is then inoperative. PA1 2--the circuit is set back to the normal operating mode. The imposed states combine to create states which are functions of the structure and of the failure or success of the logic elements of the circuit. PA1 3--all the resulting states or part of them are sampled in the testing flip-flops. PA1 4--the sampled values are extracted from the circuit by shiftings in these flip-flops, to be analyzed. PA1 it must be guaranteed that the content of the flip-flop will not be modified upon loading by shifting of the testing flip-flops, in which case this loading would be blocked as soon as the value of the programming bit would correspond to the functional mode. The flip-flop must thus be placed outside the shifting paths used for testing, PA1 it must be guaranteed that the content of the flip-flop will not be modified untimely during the testing steps performed in functional mode, PA1 an access to the flip-flop must be guaranteed to be able to modify its content, when the mode employed is desired to be modified from the outside. PA1 to insulate, when entering the test mode, a first pad from the internal elements to which it is connected in normal operating mode, these elements being connected to a second pad substituting for the first pad, and PA1 to control the exit from the test mode by this first pad, the register storing the mode implemented being on the one hand responsive to the state present thereon, and on the other hand insulated from the interface in test mode.
A problem set by the testing systems used especially is the impact of such systems on the price of the circuits, even when they are only briefly used at the beginning of the lifetime of the circuits.
The primary inputs/outputs available for the testing on a circuit are generally a rare resource, especially for circuits including few primary inputs/outputs. This problem is all the more constraining as the circuits are encapsulated in housings having a standardized number of pins. Changing the number of pins may cause a significant variation of the housing surface, and thus of the price of the circuits. Sometimes, the suppression of a single input/output may enable use of a smaller housing (it will for example be passed from 12 pins to 8 pins) and thus to decrease in a non negligible proportion the price of the circuit.
To be able to do without inputs/outputs exclusively dedicated to testing thus appears to be very advantageous.
A solution is to test the circuits only under their functional aspect, that is, practically, to use the circuit in normal operating mode in the application for which it is meant. This solution has the disadvantage of requiring a lot of time and energy to devise stimuli which ensure a satisfactory fault coverage, especially for complex circuits.
Another, widely employed, solution, is to multiplex most of the primary test inputs/outputs with functional pins, that is, a same input/output receives or provides a signal to internal elements which can be different in normal operating mode and in test mode. A single pin of the circuit is dedicated to testing to provide the signal which controls the multiplexing.
A solution for suppressing or eliminating this dedicated pin is to replace it with a programming bit representative of the mode, that is, by a flip-flop of an internal control register, programmable from the outside via an interface formed of data, address and control buses only.
This solution, of software type, has several disadvantages:
A solution to overcome these disadvantages is to insulate the interface of the circuit to be tested which is implemented to access the flip-flop. This runs the risks of a non-negligible decrease in the fault coverage because the circuit nodes connected to this interface are no longer being tested.